Book Club (COAD) – Day 19: 2.5



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0:08 Set the stage for our continuation of the book
1:00 Chapter 2.5 Representing instructions in the Computer: https://www.elsevier.com/books/computer-organization-and-design-risc-v-edition/patterson/978-0-12-812275-4
1:58 Chapter 2.5 Example 1 – Translating a RISC-V Assembly Instruction into a Machine Instruction
3:11 The decimal representation of RISC-V asm `add x9, x20, x21`
5:29 Chapter 2.5 Example 1 continued
7:34 RISC-V Instruction Encoding
10:03 The binary representation of RISC-V asm `add x9, x20, x21`
13:05 Chapter 2.5 continued, on the instruction format
13:32 A few words on RISC-V’s compressed extension
17:20 Chapter 2.5 continued, machine language and machine code
17:30 Distinguishing between assembly and machine code
19:50 Chapter 2.5 continued, hexadecimal-to-binary conversion
21:47 Hexadecimal
29:12 Chat comment: “Hello”
29:15 Binary to hexadecimal
34:40 Chat comment: “Unrelated: I am of the opinion that humans should have adopted the dozenal (base 12) system instead of base 10”
36:02 Hexadecimal to decimal conversion
37:22 Chat comment: “Yeah you can count to 12 on one hand using knuckles and your thumb to point”
39:47 Figure 2.4 – The hexadecimal–binary conversion table
42:09 Chapter 2.5 continued, subscripting the numeral system
43:46 Chapter 2.5 Example 2 – Binary to Hexadecimal and Back
44:52 Converting 0xECA86420 to binary
47:46 Chat comment: “Later, take care”
47:54 Converting 0001 0011 0101 0111 1001 1011 1101 1111 to hexadecimal
51:34 Compare our answer to Chapter 2.5 Example 2 with the book
53:33 Recommend memorising hexadecimal–binary pairings
55:55 Chapter 2.5 continued, RISC-V Fields
58:38 Note that the J-type instructions may no longer exist
1:00:35 Chapter 2.5 continued, instruction formats
1:05:14 Design Principle 3: “Good design demands compromises”
1:08:58 Design Principle 2: “Smaller is faster”
1:14:42 Design Principle 1: “Simplicity favours regularity”
1:16:30 Shout-out to RAD Game Tools’ employee Mr4thDimention and the quality of his editor 4coder
1:20:20 Chapter 2.5 continued, the compromises chosen by the RISC-V designers
1:24:14 The load register instruction from page 71: https://riscy.handmade.network/episode/coad/coad016/#2690
1:28:56 Figure 2.5 – RISC-V instruction encoding
1:32:46 Point out the versatility of the opcodes in RISC-V
1:34:57 Figure 2.5 continued
1:36:23 A few more words on the versatility and unsimplicity of opcodes
1:38:22 Chapter 2.5 Example 3 – Translating RISC-V Assembly Language into Machine Language
1:39:22 Lowering from C to assembly: `A[30] = h + A[30] + 1;`: http://www.riscvbook.com/
1:50:45 Translating our assembly to machine code
2:23:25 Thoughts on viewing RISC-V instructions
2:31:48 Continue translating our assembly to machine code
2:44:17 Compare our answer to Chapter 2.5 Example 3 with the book
3:09:26 A few words on the greater potential for errors in handwritten machine code than C
3:14:01 Chapter 2.5 Elaborations, on immediate instructions
3:15:11 Chapter 2.5 Hardware / Software Interface
3:15:40 Figure 2.6 – RISC-V architecture revealed through Section 2.5
3:18:30 Chapter 2.5 The Big Picture
3:19:58 Figure 2.7 The stored-program concept
3:21:24 Chapter 2.5 Check Yourself
3:24:41 That ends section 2.5

Annotated by Miblo – https://handmade.network/m/Miblo

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